In light of significant development of various portable products in communication, network and computer fields, ball grid array (BGA) packages with high densities and multiple contacts have become mainstream products in the semiconductor packaging field. The BGA package usually cooperates with a highly effective chip such as a microprocessor, chip set and graphic chip to achieve high speed operations. An advanced semiconductor packaging technology is employed to fabricate the BGA package, which is characterized by mounting a semiconductor chip on a front side of a substrate and implanting a grid array of solder balls on a back side of the substrate. This allows more input/output (I/O) connections to be accommodated on the same unit area of a chip carrier (e.g. the substrate) to satisfy the requirement for a highly integrated semiconductor chip, such that the entire package unit can be bonded and electrically connected to an external device by the solder balls.
In order to improve the production yield and reduce the fabrication cost for a semiconductor device, current micro semiconductor packages are mostly fabricated by a batch method as disclosed in U.S. Pat. Nos. 6,281,047, 6,319,750 and 6,479,894, etc. The batch fabrication method is implemented by firstly defining a plurality of array-arranged package units on a surface of a chip carrier via a plurality of grid-shaped boundary lines formed on the chip carrier. Then, die-bonding, wire-bonding and encapsulation processes are performed. Subsequently, a singulation process is carried out to remove a connected portion between any two adjacent package units, such that a plurality of independent semiconductor packages are fabricated. For example, a thin and fine pitch ball grid array (TFBGA) package has been proposed and is sized even smaller to satisfy the light-weight and low-profile requirements of electronic products. The TFBGA packages are fabricated on the same substrate in a batch manner. The substrate is in advance defined with a plurality of package sites thereon where a plurality of TFBGA package units are to be formed. Then, the die-bonding, wire-bonding and encapsulation processes are performed. Finally, the singulation process is carried out to separate the package sites and semiconductor chips mounted thereon from each other to form individual TFBGA package units.
Generally, for establishing electrical connection between a semiconductor package unit and an external electronic device via solder balls, or for effectively electrically connecting a semiconductor chip to a substrate in the package unit, a plurality of conductive circuits made of e.g. a copper material are formed on a surface of the substrate. A metallic layer such as a nickel/gold (Ni/Au) layer can be disposed on an exposed surface of a conductive pad extended from each of the conductive circuits. This allows other conductive elements such as gold wires, bumps or solder balls to be effectively electrically connected to the chip or substrate, and also prevents oxidation of the conductive pads due to an external environmental effect. In particular, for fabricating the highly conductive Ni/Au metallic layer, all circuit elements (e.g. the conductive pads) to be subsequently formed with the Ni/Au metallic layer thereon are connected to a plating bus during a circuit fabrication process of the substrate, such that an electroplating current can reach all the circuit elements via the plating bus to deposit the Ni/Au metallic layer on each of the circuit elements. When the packaging processes are complete, the plating bus becomes useless and should be removed.
FIG. 1 shows a semiconductor package substrate for use in batch fabrication of package units. The substrate 100 comprises a plurality of substrate units 10 that are defined and bordered by a plurality of transverse cutting lines SLx and a plurality of longitudinal cutting lines SLy formed on the substrate 100, wherein the substrate units 10 represent package sites to be subjected to subsequent packaging processes. During a final singulation process, the package sites can be separated by cutting along the cutting lines SLx and Sly to form individual package units. Each of the substrate units 10 comprises a plurality of bond pads 11, a plurality of conductive vias 12, and a plurality of conductive circuits 13 for electrically connecting the bond pads 11 to the conductive vias 12, wherein the conductive vias 12 are used to electrically connect the conductive circuits 13 on a front side of the substrate unit 10 to ball pads (not shown) on a back side of the substrate unit 10. In order to deposit a Ni/Au metallic layer on each of the bond pads 11 and ball pads on the front and back sides of the substrate unit 10 respectively by an electroplating process, the bond pads 11 and the ball pads are connected to a plating bus 14 formed around each of the package sites, such that an electroplating current can reach all the bond pads 11 and ball pads on the front and back sides of the substrate unit 10 respectively via the plating bus 14 so as to form the electroplated Ni/Au metallic layer on each of the bond pads 11 and ball pads. The plating buses 14 on the substrate 100 are grid-shaped and directly superimposed on the transverse and longitudinal cutting lines SLx and SLy, such that the plating buses 14 can be simultaneously removed by the final singulation process.
However, the above arrangement of the substrate is inherent with significant drawbacks. FIGS. 2A and 2B are cross-sectional views showing the substrate in FIG. 1 during a molding process respectively taken along lines 2A—2A and 2B—2B. After a chip 210 is mounted on and electrically connected to each of the substrate units 10, the molding process is performed using a mold 250 having an upper mold cavity 251, wherein a clamping area 252 of the mold 250 is positioned in correspondence with a predetermined mold clamp line (MCL) on the substrate 100, such that an encapsulating material 253 can be injected into the upper mold cavity 251 from a gate (not shown) so as to completely fill the upper mold cavity 251 with the encapsulating material 253. As a result, an encapsulant for encapsulating the chips 210 is formed on the substrate 100.
Generally, a solder mask layer 101 is applied on a surface of the substrate 100 and becomes contracted after being heated and cured, wherein more contraction of the solder mask layer 101 occurs at an area with no circuit being provided thereunder. Thereby, at an interface between the substrate 100 and the mold 250, a portion of the solder mask layer 101 covering circuits (i.e. the plating buses 14) becomes higher than another portion of the solder mask layer 101 not covering circuits. This results in collapse or sinking of the solder mask layer 101 between the adjacent plating buses 14. As a result, during the molding process, a gap 220 is formed between the mold 250 and the solder mask layer 101 at a position where the solder mask layer 101 collapses, and the encapsulating material 253 injected into the upper mold cavity 251 would leak through the gap 220 and cause flashes 230 (as shown in FIG. 2C). The flashes 230 not only impair the package appearance, but may further flow to another surface of the substrate 100 along positioning holes, slots or edges of the substrate 100, thereby contaminating the ball pads to be mounted with solder balls on the substrate 100 and adversely affecting the reliability of subsequent fabrication processes.
Referring to FIG. 3, in light of the above drawbacks, U.S. Pat. No. 6,692,988 has disclosed a method of forming at least one dummy trace 313 between two adjacent circuits 310 to avoid an oversized pitch between the adjacent circuits 310. For example, there are two dummy traces 313 formed within a pitch D1 between two adjacent circuits 310, such that the circuits 310 and the dummy traces 313 are evenly distributed, making a solder mask layer applied thereon substantially flat and have an equal height. Therefore, the effect of preventing flashes can be achieved.
However, the above arrangement when being applied to e.g. a TFBGA structure is not effective to completely solve the problem of flashes. This is because no matter where the dummy trace is located, a certain pitch always exists between adjacent circuits (the dummy trace and a plating bus). When the solder mask layer is applied on the plating bus and the dummy trace, there are still a plurality of collapsed portions formed therebetween, which accordingly cause a plurality of smaller gaps between the mold and the solder mask layer during the molding process. Thus, the encapsulating material having good fluidity would leak through the gaps and result in flashes. Moreover, the provision of dummy traces also leads to other drawbacks due to too many dummy traces being in advance formed on a peripheral area of the substrate for the purpose of preventing flashes. In such case, during a singulation process to simultaneously cut the dummy traces and the plating buses, excess burrs are produced and easily cause short-circuiting between adjacent circuits, thereby seriously affecting the electrical quality of a fabricated product.
Referring to FIG. 4, U.S. Pat. No. 5,744,084 has disclosed a method of forming a dam structure 420 on a surface of a substrate 408, wherein the dam structure 420 is used to accommodate a clamping area of an upper mold 402, so as to prevent the foregoing flashes. However, the dam structure 420 must be additionally fabricated after completing the circuitry of the substrate 408, and the fabrication processes of the dam structure 420 are complicated. It is therefore not cost-effective to fabricate the dam structure 420 in practice. Moreover, as various marks may usually be printed on a peripheral area of the substrate by e.g. a substrate manufacturer, the dam structure 420 that is also located on the peripheral area of the substrate would influence the performance of the mark-printing process on the substrate.
Therefore, the problem to be solved here is to provide a flash preventing substrate and a method for fabricating the same, which can eliminate short-circuiting that is possibly induced by a singulation process for a packaged structure, so as to achieve better cost effectiveness.